GPIO-MM-21

Overview

FPGA-based Reconfigurable 96-line Digital I/O

GPIO-MM-21 is part of a family of reconfigurable digital I/O and counter / timer modules with various port and pin configurations. Each board uses identical hardware with a 200K gate Xilinx Spartan II RAM-based FPGA. The varying configurations are based on different FPGA code. The FPGA code is stored in a flash memory on the board, enabling GPIO-MM-21 to be reprogrammed in the field with different designs, including custom designs.

The GPIO-MM-21 configuration provides 96 digital I/O lines. 48 lines are buffered. The 96 digital I/O lines are compatible with our legacy Garnet-MM and Onyx-MM boards. This configuration combines the features of two 48-line digital I/O boards into one board to reduce your PC/104 stack size and cost.

Other GPIO-MM configurations provide 48 digital I/O lines with 10 16-bit counter/timers.

Digital I/O Features

The digital I/O includes 96 programmable-direction lines using four 8255 cores. 48 of the I/O lines are buffered for enhanced output current. All I/O lines contain jumper-selectable 10Kohm pull-up/pull-down resistors. 48 I/O lines are contained on each of two 50-pin connectors, along with system ground and a convenient +5V power pin. Both I/O connectors provide the digital I/O lines in ABC port order.

Miscellaneous Features

The board requires only a +5V input and operates from -40°C to +85°C. All board functions are supported by our Universal Driver software for Linux, Windows 2000/XP/CE, DOS, and QNX.