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Reconfigurable 48-line Digital I/O + Counter/Timer PC/104 Module

GPIO-MM-12

FPGA-based Reconfigurable 48-line Digital I/O + Counter/Timer PC/104 Module

Description

Overview

FPGA-based Reconfigurable 48-line Digital I/O

GPIO-MM-12 is part of a family of reconfigurable digital I/O and counter / timer modules with various port and pin configurations. Each board uses identical hardware with a 200K gate Xilinx Spartan II RAM-based FPGA. The varying configurations are based on different FPGA code. The FPGA code is stored in a flash memory on the board, enabling GPIO-MM-12 to be reprogrammed in the field with different designs, including custom designs.

The GPIO-MM-12 configuration provides 48 digital I/O lines and 10 programmable counter/timers. The counter/timer features are based on our legacy Quartz-MM board, while the 48 digital I/O lines are compatible with our legacy Garnet-MM board. This configuration combines the features of both these boards into one board to reduce your PC/104 stack size and cost.

Other GPIO-MM configurations provide up to 96 digital I/O lines.

Counter/Timer Features

The 10 16-bit counter/timers are provided by two 9513 cores. The high speed FPGA enables a fast 40MHz clock input, providing greater precision in timing applications. The counters can be joined under software control to provide 32-bit, 48-bit or 64-bit counters. A variety of input, gate, and output features are available to implement a wide range of waveform, counting, and timing functions. The counter / timer I/O connector uses the same pinout as the connector for Quartz-MM 10-channel boards and includes 16 digital I/O lines configured as 8 inputs and 8 outputs. The fixed I/O and the counter/timer signals feature ESD-protective circuitry.

Digital I/O Features

The digital I/O includes 48 programmable-direction lines using two 8255 cores. All I/O lines are buffered for enhanced output current. All I/O lines contain jumper-selectable 10Kohm pull-up/pull-down resistors. The 48 I/O lines are contained on a single 50-pin connector, along with system ground and a convenient +5V power pin. The I/O connector presents the digital I/O lines in ABC port order.

ISA Bus Interrupts

GPIO-MM-12 offers two user-programmable interrupt circuits. Possible uses include timer based interrupts or interrupts driven by external signals.

Miscellaneous Features

GPIO-MM-12 includes a 256-byte EEPROM for general-purpose non-volatile storage of user application data. Easy register-level access to the EEPROM simplifies use of this valuable feature.

The board requires only a +5V input and operates from -40°C to +85°C. All board functions are supported by our Universal Driver software for Linux, Windows 2000/XP/CE, DOS, and QNX.

Specifications

Base FPGA Xilinx Spartan II, 200,000 gates, 40K RAM bits
Input clock 40MHz
FPGA code storage Flash memory, field upgradeable via JTAG
ID indicator 8-bit LED display indicates FPGA code personality
No. of I/O pins 100 pins (48 buffered)
Programmable Digital I/O 48 using 8255 cores
Fixed Direction I/O 8 fixed inputs and 8 fixed outputs
Counter/timers 10 16-bit, using 9513 cores
Max counting freq 40MHz
Counter modes Counter, rate/square-wave generator, pulse-width modulator, programmable one-shot, hardware/software triggered strobe
Output current, buffered I/O Logic 0: 64mA max per line
Ouptut current, 
fixed I/O and fixed counter/timers
±24mA max
Dimensions 3.55" x 3.775", PC/104 form factor
PC/104 bus 16-bit stackthrough ISA bus
Power supply +5VDC ±5%
Operating temperature -40°C to +85°C standard, all versions
RoHS Compliant

Ordering

Available Models:
GPIO-MM-12-XT 48 Digital I/O plus 10 Counter/Timers PC/104 Module
C-50-18 50-conductor .1" pitch 18" ribbon cable Data Acquisition

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By Phone

Main: 604.814.5069
Fax: 888.831.5149

By Mail

Tri-M Technologies Inc.
208 – 31510 Gill Avenue
Mission, BC, Canada  V4S 0A1

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