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Reconfigurable 48-line Digital I/O + Counter/Timer PC/104 Module

GPIO-MM

FPGA-based Reconfigurable 48-line Digital I/O + Counter/Timer PC/104 Module

Description

Overview

FPGA-based Reconfigurable 48-line Digital I/O

GPIO-MM is a PC/104 digital I/O module based on an FPGA, allowing multiple feature sets to be implemented on the same hardware platform. The FPGA is a Xilinx Spartan 2 RAM-based device with 200K gates (XC2S200). An on-board configuraton flash memory device stores the FPGA code for automatic loading on power-up, and new code can be downloaded using a JTAG cable connected to a PC. Several standard off the shelf personalities are available, and custom ones can be developed either by users with Xilinx tools or by Diamond as a customization service.

The right side I/O connector includes ESD protection circuitry for increased reliability, while the left side I/O connector offers high-drive logic buffers for increased load compatibility, along with jumper-configured pull-up / pull-down resistors. All digital I/O pins are set to input on power-up to avoid conflicts with external circuitry.

Hardware configuration options include jumper-selectable base address and DMA level, plus a 10-position jumper lock for user-definable field configurability when used with custom designs. A 256-byte EEPROM provides convenient non-volatile storage for user-defined functionality. The board also includes the layout for an optional RS-232/422/485 serial port, so that a multi-protocol serial port can be integrated into custom designs.

GPIO-MM contains 8 diagnostic LEDs located in the lower left corner. Off-the-shelf configurations use these LEDs to identify the personality programmed onto the board, while custom designs can use them for any purpose. An additional programmable LED in the lower right corner offers a simple way to verify successful FPGA programming.

Standard feature sets include:

  1. 10 "9513" style 16-bit counter/timers + 8 fixed digital inputs + 8 fixed digital outputs + 48 buffered programmable digital I/O
  2. 48 programmable digital I/O + 48 buffered programmable digital I/O

9513 Counter/Tmers
The GPIO-MM code includes two 9513 counter/timer cores, each containing 5 16-bit counters. This core is based on the popular high performance AMD9513 counter/timer IC. These counters offer extreme flexibility, with programmable input sources, programmable output waveforms, programmable up / down count, one-shot vs. continuous counting, PWM function, and more. Counters can be cascaded together to form 32-bit, 48-bit, etc. wide counters. An input clock of 40MHz provides fine resolution for timing applications.

Specifications

Base FPGA Xilinx Spartan II, 200,000 gates, 40K RAM bits
Input clock 40MHz
FPGA code storage Flash memory, field upgradeable via JTAG
ID indicator 8-bit LED display indicates FPGA code personality
No. of I/O pins 100 pins (48 buffered)
Programmable Digital I/O 48 using 8255 cores
Fixed Direction I/O 8 fixed inputs and 8 fixed outputs
Counter/timers 10 16-bit, using 9513 cores
Max counting freq 40MHz
Counter modes Counter, rate/square-wave generator, programmable one-shot, 
hardware/software triggered strobe
Output current, buffered I/O Logic 0: 64mA max per line
Ouptut current, 
fixed I/O and fixed counter/timers
±24mA max
Dimensions 3.55" x 3.775", PC/104 form factor
PC/104 bus 16-bit stackthrough ISA bus
Power supply +5VDC ±5%
Operating temperature -40°C to +85°C standard, all versions
RoHS Compliant

Ordering

Available Models:
GPIO-MM-XT 48 Digital I/O plus 10 Counter/Timers PC/104 Module
C-50-18 50-conductor .1" pitch 18" ribbon cable Data Acquisition

By Email

By Phone

Main: 604.814.5069
Fax: 888.831.5149

By Mail

Tri-M Technologies Inc.
208 – 31510 Gill Avenue
Mission, BC, Canada  V4S 0A1

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